The present invention is related to field programmable integrated circuits, and more particularly, to Field Programmable Gate Arrays (FPGAs).
Typically, an FPGA has an array of logic elements and wiring interconnections with many thousands, or even hundreds of thousands, of programmable interconnects so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection, or to set the function or functions of a logic element.
FPGAs use either memory cells or antifuses for the programmable switches. The memory cells are reprogrammable and antifuses are programmable only once. In U.S. Ser. No. 08/270,714, entitled, "A GENERAL PURPOSE, NON-VOLATILE REPROGRAMMABLE SWITCH," filed Jul. 5, 1994 by Robert J. Lipp, Richard D. Freeman, Robert U. Broze, John M. Caywood, and Joseph G. Nolan, III, and assigned to the present assignee, a new memory-type of programmable interconnect is disclosed. The described FPGA programmable interconnect has a non-volatile memory (NVM) cell, which is reprogrammable, to provide a general purpose switching element to randomly interconnect the FPGA wiring and circuit elements.
The present invention provides for an improvement in the disclosed programmable interconnect. In particular, the process of manufacturing the programming portion of the programmable interconnect is improved with the resulting programming element, an EPROM transistor cell, having improved electrical operating parameters.